1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive structures in dielectric layers on an integrated circuit devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of field effect transistors (NMOS and PMOS transistors) that substantially determine performance of the integrated circuits. Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the transistors and the overall functionality of the circuit. Given that the channel length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of additional techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of highly-conductive copper lines and vias to provide electrical wiring connections to the transistors, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors).
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Generally, as the device dimensions have decreased, the physical size of the conductive interconnections, e.g., metal lines and metal vias formed in multiple metallization layers above the device level, have also become smaller. Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than 3) and “ultra-low-k” (ULK) dielectric materials (materials having a dielectric constant less than 2.7) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using tungsten for the conductive lines and vias. The use of low-k and ULK dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants.
However, the use of such ULK dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials. As one example, ULK materials tend to have less mechanical strength than other, higher-k value materials, such as silicon dioxide. Another problem associated with the use of some dielectric materials, such as, for example, ULK materials, is that such materials are subject to being damaged during processing operations. FIG. 1 depicts an illustrative prior art metallization layer 100. The metallization layer 100 generally comprises a plurality of schematically depicted conductive lines 14 and a conductive via 16 formed in an illustrative ULK layer 10. Also depicted in FIG. 1 is an illustrative layer 12 that acts to passivate underlying conductive lines (not shown) formed in the metallization layer (not shown) formed below the metallization layer 100 depicted in FIG. 1. The layer 12 may also perform other functions such as acting as a stop layer for a chemical mechanical polishing (CMP) operation performed on the underlying metallization layer. The conductive lines and vias 14, 16 may be made of a variety of materials, such as copper, tungsten, etc., and they may be formed by performing a variety of known techniques. One illustrative process flow would include the following steps: (1) deposit the ULK layer 10; form a hard mask material (not shown in FIG. 1) above the ULK layer 10; (3) form a patterned resist mask (not shown) above the hard mask layer; (4) perform one or more etching processes to define various openings in the UKL layer 10; (5) strip the photoresist mask, typically by performing a plasma-based stripping or so-called ashing process; (6) form the appropriate conductive materials in the openings in the ULK layer 10 (such as by forming one or more barrier layers and thereafter blanket-depositing a conductive material in the openings in the ULK layer 10).
The resist stripping process tends to damage the ULK layer 10 as schematically depicted by the damaged regions 18 shown in FIG. 1. The extent and amount of such damage may vary depending upon the particular application. Moreover, in some cases the damaged regions 18 may not be uniform for all openings, as reflected in FIG. 1. The thickness of the damaged regions 18 can also vary depending upon the particular application and the particular ULK material 10 being used. In one example, the damaged regions 18 may have a thickness 19 that ranges from 5-40 nm. The damaged regions 18 may reflect a loss of ULK material, a formation of air gaps in the ULK material and/or an undesirable, localized increase in the k value of the ULK material. In some cases, the k value of the damage regions 18 can exhibit be increased by about 10-50%, relative the un-damaged ULK material. Such localized increased in k value due to the damaged regions 18 may undesirably increase the overall k value of the ULK layer 10, thereby tending to reduce the desired insulating characteristics of the overall ULK layer 10, which may lead to a decrease in the electrical performance characteristics a resulting integrated circuit device incorporating the metallization layer 100.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.